1. Field of the Invention
The invention relates to memories, and more particularly to flash memories.
2. Description of the Related Art
A flash memory comprises a plurality of blocks. Each block comprises a plurality of pages for data storage. When the flash memory receives a write command from a controller, the flash memory must write received data to at least one block thereof according to a write address. When the flash memory receives a read command from the controller, the flash memory must read data from at least one block thereof according to a read address.
When a page of a flash memory stores data, the page cannot be written with new update data before the original data stored in the page is erased. Because a flash memory erases data in a unit of a block, the data stored in all pages of a block must be erased together. Thus, erasing data from a block requires a long time period, and a controller cannot erase data from a flash memory with a high frequency.
When a host sends a write command to a controller to write new data to a write address, if the pages of a target block corresponding to the write address store original data, the controller cannot directly write the new data to the pages of the target block. The controller, however, must execute the write command received from the host. The controller therefore obtains a spare block from the flash memory to store the new data. Because the new data stored in the spare block is mapped to the write address as the original data stored in the target block, there is a mapping relationship between the target block and the spare block. The target block is therefore referred to as a mother block, and the spare block is therefore referred to as a child block mapped to the mother block for storing update data for the mother block.
Referring to FIG. 1, a mother block 102 and a child block 104 of a conventional mapping relationship is shown. The mother block 102 comprise pages mapped to a logical address range of 0˜1000 and has original data A0, B0, C0, and D0 stored therein. When a host sends a first write command to a controller to request the controller to write update data B1 to the address range 400˜600, the space corresponding to the address range 400˜600 in the mother block 102 has stored original data B0 and cannot store the update data B1. The controller then selects a spare block from the flash memory as the child block 104 mapped to the mother block 102, copies the data A0 corresponding to an address range 0˜400 to the address range 0˜400 of the child block 104, and writes the update data B1 to the address range 400˜600 of the child block 104. Similarly, if the host sends a second write command to the controller to request the controller to write update data C1 to an address range 601˜700, because the space corresponding to the address range 601˜700 in the mother block 102 has stored original data C0, the controller directly writes the update data C1 to the address range 601˜700 of the child block 104.
If the host sends a third write command to the controller to request the controller to write new data to an address range 0˜700, because the space corresponding to the address range 0˜700 in the child block 105 has stored data A0 and update data B1 and C1, the controller cannot write the new data to the child block 104 to execute the third write command of the host. Thus, a data access method of a flash memory is required to solve the aforementioned problem.